Partial-Scan testing has shown much promise for solving the problem of testing large and complex integrated circuits. As taught in U.S. Pat. No. 5,043,986, issued on Aug. 27, 1991, in the names of V. D. Agrawal and K. Cheng, and assigned to AT&T (herein incorporated by reference), an integrated circuit, containing flip-flops and combinational logic elements, can be Partial-Scan tested by first isolating a small set of flip-flops, referred to as "scan" flip-flops. The scan flip-flops are selected such that while the integrated circuit is in a test mode, substantially all feedback paths equal to or greater than a prescribed cycle length are eliminated. A feedback path is defined as a signal path from a flip-flop output to one of its inputs whereas the cycle length is defined as the number of non-scan flip-flops in such a feedback path. Once selected, the scan flip-flops are configured in one or more chains.
To accomplish Partial-Scan testing, each chain of scan flip-flops is loaded with test data while the remainder of the integrated circuit is placed in a non-operational mode (i.e., the non-scan flip-flops are disabled). At the outset of testing, the integrated circuit is placed in a "scan" mode during which test data is loaded into the scan flip-flops and any old data present therein is shifted out. Thereafter, the integrated circuit is placed in an "apply" mode for a brief interval (wherein all scan and non-scan flip-flops are clocked) to allow the circuit to react to the test data loaded into the scan flip-flop chains as well as externally applied test data. As a consequence, new data may be present for loading into the scan flip-flops. Then, the integrated circuit returns to the "scan" mode and the data present in the scan flip-flop chains are shifted out for analysis while new test values are shifted in.
Partial-Scan testing of an integrated circuit in the manner described above is typically controlled in accordance with three separate control signals: PS.sub.-- CLOCK, MODE and TEST.sub.-- EN. The PS.sub.-- CLOCK signal is a clock signal that clocks the scan flip-flops during the scan mode as well as during the apply mode so that the scan flip-flops can scan in test data and also capture the responses to such test signals. The TEST.sub.-- EN signal controls the operating state of the integrated circuit in order to render the circuit testable by the Partial-Scan testing technique. In this regard, the TEST.sub.-- EN signal blocks the asynchronous preset and clear inputs of the non-scan flip-flops and blocks the passage of the operating clock signals to the combinational elements during testing. Also, the TEST.sub.-- EN signal disables the system clock signals to the scan flip-flops. The MODE signal controls the shifting of test data into and out of the integrated circuit by controlling each of a set of multiplexers, each placed upstream of a separate one of the scan flip-flops in each chain so as to control the passage of signals through the chain of scan flip-flops. The MODE signal also controls a set of multiplexers that multiplex the output data from the integrated circuit. For an integrated circuit to undergo Partial-Scan testing, the above-described Partial-Scan control signals PS.sub.-- CLOCK, TEST.sub.-- EN and MODE must be present. In the past, an external test system generated these control signals and supplied them to the integrated circuit via a separate one of three inputs (i.e., pins) to the circuit dedicated for this purpose.
In addition to being configured for Partial-Scan testing, an integrated circuit may also be configured for Boundary-Scan testing in accordance with the IEEE 1149.1 Boundary-Scan standard (May 21, 1990), described in the publication IEEE Standard Test Access Port and Boundary-Scan Architecture, published by the IEEE, Piscataway, N.J. (herein incorporated by reference). To be Boundary-Scan compliant in accordance with the IEEE 1149.1 standard, an integrated circuit must have a Test Access Port (TAP) provided with a Test Data Input (TDI), a Test Clock (TCK) input, a Test Mode Select (TMS) input and a Test Data Output (TDO). Optionally, the TAP may include a Test Reset (TRST) input as well. Thus, at least four dedicated pins are required for Boundary-Scan compliance. In order to facilitate both Partial-Scan testing and Boundary-Scan testing, the integrated circuit must possess seven dedicated pins for test purposes, four for Boundary-Scan and three for Partial-Scan.
The need to dedicate at least seven pins of the integrated circuit for testing purposes reduces the number of pins available for normal (i.e., non-test) operation. Thus, there is a need for a technique for carrying out Boundary-Scan testing and Partial-Scan testing of an integrated circuit while reducing the number of pins required for testing purposes.